Analog Verification Jobs

Senior Hardware Design Engineer role focused on ASIC/FPGA/SoC design, verification, and physical implementation for a cleared government-contractor environment.

Marvell is hiring a Staff Analog Layout Engineer in Santa Clara to lead layout and verification of high-speed and precision analog IP using Cadence Virtuoso across multiple process nodes.

Support Rolls‑Royce electrical engineering teams in Indianapolis to design, implement and verify embedded electronics for military and aerospace systems during a paid 12‑week internship.

Lead and mentor an analog engineering team at Renesas CMSD to define architectures, drive analog/mixed-signal ASIC design and verification, and deliver highly configurable products to market.

Marvell is hiring a Senior Staff Analog Layout SRAM Engineer in Burlington, VT to lead SRAM memory layout and sign-off verification efforts and drive automation and quality across custom memory designs.