Cadence Virtuoso Jobs

Marvell is hiring a Staff Analog Layout Engineer in Santa Clara to lead layout and verification of high-speed and precision analog IP using Cadence Virtuoso across multiple process nodes.

Lead the architecture, RTL, verification, and silicon bring-up of mixed-signal ASICs that power Atom Computing’s neutral-atom quantum computers while shaping the long-term silicon roadmap.

Senior engineer to build and own SPICE simulation flows and Virtuoso-based CAD automation that accelerate analog/mixed-signal design productivity and improve simulation-to-silicon correlation.

Inclusive & Diverse

Rise from Within

Mission Driven

Diversity of Opinions

Work/Life Harmony

Growth & Learning

Transparent & Candid

Customer-Centric

Snacks

Onsite Gym

Family Coverage (Insurance)

Medical Insurance

Dental Insurance

Vision Insurance

Mental Health Resources

Life insurance

Disability Insurance

Health Savings Account (HSA)

Flexible Spending Account (FSA)

Learning & Development

Paid Time-Off

401K Matching

Maternity Leave

Paternity Leave

Become a key contributor on Intel's DTP team building and automating density/fill solutions and PDK fill components to ensure manufacturability at advanced semiconductor nodes.

Cadence is hiring a Solutions Architect (AE) to lead PDK/technology file development and provide technical and business-facing support to semiconductor customers working on advanced process nodes.

Marvell is hiring a Senior Staff Analog Layout SRAM Engineer in Burlington, VT to lead SRAM memory layout and sign-off verification efforts and drive automation and quality across custom memory designs.

Experienced DRAM design engineer needed to drive circuit design, simulation, and layout leadership for advanced memory products at Micron's Richardson site.