Principal ASIC Physical Design Engineer
Skills
- End-to-end RTL-to-GDSII physical design expertise using Synopsys/Cadence/Siemens flows
- Proven timing closure and static timing analysis experience for complex multi-clock SoCs
- Hands-on experience with advanced FinFET process nodes and sign-off flows
- Experience with IR drop analysis, ECO implementation, power domain (UPF/CPF) integration
- Vendor and offshore PD team management experience and strong cross-functional communication
Responsibilities
- Own full RTL-to-GDSII flow: synthesis, floorplanning, place & route, CTS, STA, physical verification, and sign-off.
- Develop and maintain physical design methodologies, scripts, and automation to optimize PPA.
- Drive timing closure across multiple voltage/process corners and perform IR-drop analysis and ECOs.
- Partner with package, SI/PI, test, and post-silicon teams for package-aware floorplanning and chip bring-up.
- Manage and technically guide external physical design partners and offshore vendors.
- Work with EDA vendors to debug and optimize tool flows and evaluate new methodologies.
- Support production and spaceflight lifecycle for ASICs, including tapeout coordination and vendor management.
- Mentor and grow the physical design team; act as technical SME across cross-functional teams.
Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field required
- Master's degree preferred but not required
Benefits
- Base salary range $190,000–$280,000 plus equity
- Comprehensive medical, dental, and vision coverage
- Paid time off and paid parental leave
- Life insurance and other standard benefits
- Opportunities to work on spaceflight-bound hardware and fast-paced product launches
- Remote work flexibility and collaboration with a distributed, high-impact team
Average salary estimate
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