Asic Jobs
Browse 30 exciting jobs hiring in Asic now. Check out companies hiring such as Etched, Architect, PDDN INC. in Mobile, Irvine, Birmingham.
Etched seeks a Technical Program Manager, Infrastructure to lead cross-disciplinary program delivery and vendor coordination for its ASIC, hardware, and software integration initiatives in San Jose.
Lead go-to-market for a deep-tech AI-for-chip startup by building the commercial team, closing high-ticket silicon and IP engagements, and leveraging an existing semiconductor network.
Lead verification efforts for ARM-based CPU, GPU and debug IP blocks in a remote contract role, owning verification plans, UVM environments, testcases and coverage to ensure high-quality SoC designs.
Senior Hardware Design Engineer role focused on ASIC/FPGA/SoC design, verification, and physical implementation for a cleared government-contractor environment.
Analog Devices is hiring a Staff AI/ML Digital Design Engineer to lead complex RTL design work while embedding AI/ML-driven automation into digital design flows.
Drive go-to-market strategy and customer engagements for Cadence’s agentic AI and LLM-enabled EDA products as a technically deep, business-savvy Lead Product Engineer.
K2 Space is hiring a Principal ASIC Package Design Engineer to lead FC-BGA and MCM package architecture, vendor qualification, and production ramp for high-power satellite ASICs.
K2 Space is hiring a Senior ASIC Package Design Engineer to define and deliver FC-BGA and MCM package architectures for high-pin-count, high-performance ASICs in a Series C space startup.
MicroVision is hiring a Senior RTL Engineer to design, implement, verify, and bring-up FPGA/RTL features for market-leading automotive LiDAR systems.
Lead verification for next-generation space-qualified ASICs and FPGAs on SpaceX's Starshield program, developing SystemVerilog/UVM testbenches, driving coverage closure, and supporting pre/post-silicon bring-up.
Lead RTL‑to‑GDSII implementation and advance physical design methodology for high‑performance processor and networking ASICs at Marvell's Westborough physical design team.
Lead and grow a chiplet verification team at Intel, driving verification strategy and execution for complex ASIC/SoC products using advanced verification methodologies.
Senior ASIC Design Engineer for Starshield to architect, implement, verify, and bring up high-performance ASIC/FPGA designs that support national security space and ground systems.
Lead full-chip and block-level physical implementation of advanced SoCs that power K2's high-power satellites, from synthesis through GDSII and sign-off.
Lead end-to-end physical design for cutting-edge SoCs at a high-growth Series C space company building the most powerful satellites in orbit.
Lead the architecture, RTL, verification, and silicon bring-up of mixed-signal ASICs that power Atom Computing’s neutral-atom quantum computers while shaping the long-term silicon roadmap.
Lead and mentor an analog engineering team at Renesas CMSD to define architectures, drive analog/mixed-signal ASIC design and verification, and deliver highly configurable products to market.
Lead development of verification tooling and CI infrastructure to accelerate High-Speed IO ASIC verification for NVIDIA's GPU teams.
Intel is hiring a Design Engineer focused on neuromorphic computing to develop RTL, prototype on FPGA/emulation platforms, and collaborate across architecture, verification, and software teams to bring neuro-inspired silicon to product readiness.
Lead the design and delivery of high-performance, space-qualified ASICs and FPGAs for SpaceX's Starshield national security programs.
Join Cadence’s elite verification field team to lead emulation and FPGA prototyping deployments, drive technical evaluations, and deliver customer-facing solutions using Palladium and Protium.
SpaceX Starshield is hiring a Principal ASIC Design Verification Engineer to lead SystemVerilog-based verification, drive test plans and regressions, and support pre- and post-silicon validation of next-generation space-qualified ASICs.
SpaceX Starshield is hiring a Senior ASIC Design Engineer to develop and verify next-generation FPGA/ASIC solutions for national-security space and ground systems.
SpaceX Starshield is hiring a Sr. ASIC Design Verification Engineer to lead SystemVerilog-based verification and validation of next-generation space and ground ASICs/FPGAs for national security applications.
Lead systems-level architecture and program execution for advanced oximetry and wearable monitoring products at Medtronic’s Lafayette, CO site, spanning custom silicon, embedded firmware, signal processing, and device software.
Software Engineer needed to adapt COTS protocols and develop Windows/C# (or Java-to-C#) software for classified environments, requiring active TS/SCI with polygraph.
Lead the architecture and implementation of low-latency FPGA control systems at Rigetti, designing waveform engines, DSP pipelines, and high-speed I/O for quantum processors.
Tenstorrent is hiring a Signal Integrity Engineer to drive high-speed PCB and package design, simulation, and validation for next-generation AI processors across Santa Clara, Austin, or Toronto.
Work on cutting-edge RF/analog IC design for Starlink, developing and characterizing SiGe/CMOS RFICs used in space and ground infrastructure.
SpaceX is hiring Fall 2026 software engineering interns to work onsite at U.S. sites on software projects that directly support Starship, Starlink, Dragon, Falcon and other critical programs.
