Sr. ASIC Design Engineer (Starshield) - job 2 of 2
Skills
- RTL implementation experience (Verilog/SystemVerilog)
- ASIC and FPGA development and integration
- Timing closure, synthesis, and constraint development
- Experience with EDA tool flows (simulators, lint, FPGA toolchains)
- Scripting for automation and verification (Python, TCL)
- Knowledge of bus protocols (AXI, AHB) and embedded processors
- High-speed and low-power design techniques
- Clock domain crossing mitigation and power optimization
Responsibilities
- Design digital ASICs and FPGAs, defining micro-architecture and implementing RTL in Verilog/SystemVerilog.
- Evaluate architectural trade-offs and derive subsystem and circuit specifications with cross-discipline teams (modem/DSP, RFIC).
- Integrate IP into top-level designs and deliver synthesis- and timing-clean, fully verified RTL.
- Collaborate with verification teams to ensure comprehensive coverage and verification of designs.
- Provide timing constraints and support physical implementation (synthesis, timing closure, formality checks).
- Participate in silicon bring-up, validation, and development of automated lab test equipment.
- Support off-site testing and travel as required to validate hardware.
Education
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science (required)
- Advanced degree (MS/PhD) in related field (preferred)
Benefits
- Competitive base salary with potential long-term incentives (equity/stock options or cash awards)
- Medical, vision, and dental coverage
- 401(k) retirement plan
- Short- and long-term disability insurance and life insurance
- Paid parental leave, paid vacation (approx. 3 weeks) and 10+ paid holidays
- Employee Stock Purchase Plan and potential discretionary bonuses
- Access to other company discounts and perks
Average salary estimate
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