Rtl Jobs
Browse 34 exciting jobs hiring in Rtl now. Check out companies hiring such as WHOOP, SEC, Architect in Houston, Las Vegas, New York.
WHOOP seeks an iOS Engineer II in Boston to develop shared frameworks, design-system components, and internationalization capabilities for its global client platform.
Lead the design and RTL implementation of GPU power-management blocks at Samsung Austin, translating microarchitecture into robust, production-ready hardware and partnering closely with SoC and firmware teams.
Lead go-to-market for a deep-tech AI-for-chip startup by building the commercial team, closing high-ticket silicon and IP engagements, and leveraging an existing semiconductor network.
Lead verification efforts for ARM-based CPU, GPU and debug IP blocks in a remote contract role, owning verification plans, UVM environments, testcases and coverage to ensure high-quality SoC designs.
Analog Devices is hiring a Staff AI/ML Digital Design Engineer to lead complex RTL design work while embedding AI/ML-driven automation into digital design flows.
Work on CPU pre-silicon validation and post-silicon debug for high-performance, power-efficient cores in Intel's Folsom CPU design team.
Lead WHOOP's Translations Platform team to build reliable localization infrastructure and tooling that enables rapid, high-quality language expansion across mobile, web, and backend services.
Analog Devices is hiring a Digital Design Engineer to architect and verify low-power, high-speed SerDes digital IP and mixed-signal block designs for advanced semiconductor products.
MicroVision is hiring a Senior RTL Engineer to design, implement, verify, and bring-up FPGA/RTL features for market-leading automotive LiDAR systems.
Intel is hiring a seasoned CPU RTL Design Engineer to drive RTL development, optimization, and microarchitectural specification for cutting-edge processor IP.
Lead verification for next-generation space-qualified ASICs and FPGAs on SpaceX's Starshield program, developing SystemVerilog/UVM testbenches, driving coverage closure, and supporting pre/post-silicon bring-up.
Lead RTL‑to‑GDSII implementation and advance physical design methodology for high‑performance processor and networking ASICs at Marvell's Westborough physical design team.
Lead power analysis and low‑power RTL optimization efforts at Intel to reduce dynamic and leakage power and improve overall CPU power efficiency.
Senior ASIC Design Engineer for Starshield to architect, implement, verify, and bring up high-performance ASIC/FPGA designs that support national security space and ground systems.
Intel Foundry is hiring a Physical Design Methodology and Automation Engineer to drive TFM development, regression automation, and physical design optimizations for high-performance SoC and IP implementations.
Lead end-to-end physical design for cutting-edge SoCs at a high-growth Series C space company building the most powerful satellites in orbit.
Lead the architecture, RTL, verification, and silicon bring-up of mixed-signal ASICs that power Atom Computing’s neutral-atom quantum computers while shaping the long-term silicon roadmap.
Intel is hiring a Design Engineer focused on neuromorphic computing to develop RTL, prototype on FPGA/emulation platforms, and collaborate across architecture, verification, and software teams to bring neuro-inspired silicon to product readiness.
Lead the design and delivery of high-performance, space-qualified ASICs and FPGAs for SpaceX's Starshield national security programs.
Cadence is hiring a Senior Principal IC Design Verification Application Engineer to lead customer-facing verification solutions using Xcelium and Verisium, solving complex verification challenges for top semiconductor customers.
SpaceX Starshield is hiring a Principal ASIC Design Verification Engineer to lead SystemVerilog-based verification, drive test plans and regressions, and support pre- and post-silicon validation of next-generation space-qualified ASICs.
SpaceX Starshield is hiring a Senior ASIC Design Engineer to develop and verify next-generation FPGA/ASIC solutions for national-security space and ground systems.
SpaceX Starshield is hiring a Sr. ASIC Design Verification Engineer to lead SystemVerilog-based verification and validation of next-generation space and ground ASICs/FPGAs for national security applications.
Lead the design and build-out of Sygaldry's distributed simulation and emulation platform (ASTRA-sim) to accelerate quantum-AI system modeling and integration.
Lead the microarchitecture, RTL design, and front-to-back implementation of complex SoC subsystems at a VC-backed semiconductor startup advancing next-generation chiplet solutions.
Senior RTL Design Engineer needed to develop and optimize RTL for Intel's next-generation CPU microarchitecture, driving high-performance and power-efficient processor features.
Intel's ACE organization is hiring a Design Verification Engineer to create and execute UVM/SystemVerilog verification environments for next-generation CPU designs.
Mythic seeks a Senior Silicon Emulation Engineer to develop and operate large-scale emulation platforms for AI accelerators and enable early software and performance validation before silicon.
Mach Industries is hiring an FPGA Engineer to architect, implement, and verify FPGA/SoC logic that powers next-generation autonomous defense platforms in Huntington Beach.
Help improve Intel silicon quality as an early-career DFT Design Engineer working on RTL DFT features, test strategies, and manufacturing test content for SoC and IP blocks.
CX2 is hiring an FPGA Engineer in El Segundo to develop and optimize FPGA-based solutions for real-time radar, EW, and communications systems.
Lead CPU Logic Design Engineer role at Intel driving RTL and microarchitecture development to deliver high-performance, low-power CPU features for SoC integration.
OpenAI is hiring a Senior Software Engineer to build and scale the localization and internationalization platform that delivers high-quality multilingual user experiences across products.
Lead firmware development for a novel photonic LLM accelerator at a Series A startup, owning low-level embedded software, toolchains, and hardware-software co-design.
