Sr. ASIC Design Verification Engineer (Starshield) - job 2 of 2
Skills
- SystemVerilog testbench and verification experience
- Experience with UVM/OVM/VMM methodologies
- Constrained-random verification and coverage-driven verification
- Scripting and automation with Python and MATLAB
- RTL understanding for debug and bring-up
- Strong object-oriented programming and coding skills
- Experience with regressions, coverage analysis, and closure
Responsibilities
- Lead digital ASIC verification at block and system level
- Develop, execute, and own verification test plans and milestones
- Design SystemVerilog testbench infrastructure (UVM and non-UVM), including DSP block testing
- Run regressions and drive code and functional coverage closure
- Automate test case generation and verification flows using Python and MATLAB
- Contribute to pre-silicon verification, chip bring-up, and post-silicon validation
- Debug complex RTL and verification failures and iterate rapidly to deliver operational capability
Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science (required)
- Advanced degree (MS/PhD) in related field preferred
Benefits
- Base salary $160,000 - $225,000 per year with potential clearance differential
- Long-term incentives (stock, options, or cash awards) and ESPP
- Potential discretionary bonuses
- Comprehensive medical, vision, and dental coverage
- 401(k) retirement plan
- Short and long-term disability and life insurance
- Paid parental leave
- Approximately 3 weeks paid vacation and 10+ paid holidays per year
- Accrued paid sick leave and various employee discounts
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