Systemverilog Jobs
Browse 35 exciting jobs hiring in Systemverilog now. Check out companies hiring such as Hewlett Packard Enterprise, Micron, Intel in Rancho Cucamonga, Oxnard, Des Moines.
HPE is hiring a VLSI Engineer II in Sunnyvale to develop and verify RTL modules and testbenches, leveraging SystemVerilog and verification methodologies to drive ASIC/subsystem validation.
Senior Design Engineer role at Micron to lead functional verification efforts for non-volatile memory designs using SystemVerilog, UVM, assertions and automation.
Intel is hiring a GPU Power Architect to design energy-efficient GPU architectures and power models that optimize performance-per-watt for datacenter and AI workloads.
Lead the design and RTL implementation of GPU power-management blocks at Samsung Austin, translating microarchitecture into robust, production-ready hardware and partnering closely with SoC and firmware teams.
Lead verification efforts for ARM-based CPU, GPU and debug IP blocks in a remote contract role, owning verification plans, UVM environments, testcases and coverage to ensure high-quality SoC designs.
Senior Hardware Design Engineer role focused on ASIC/FPGA/SoC design, verification, and physical implementation for a cleared government-contractor environment.
Analog Devices is hiring a Staff AI/ML Digital Design Engineer to lead complex RTL design work while embedding AI/ML-driven automation into digital design flows.
Work on CPU pre-silicon validation and post-silicon debug for high-performance, power-efficient cores in Intel's Folsom CPU design team.
Drive go-to-market strategy and customer engagements for Cadence’s agentic AI and LLM-enabled EDA products as a technically deep, business-savvy Lead Product Engineer.
Analog Devices is hiring a Digital Design Engineer to architect and verify low-power, high-speed SerDes digital IP and mixed-signal block designs for advanced semiconductor products.
A hands-on Junior CPU Design Verification Engineer role at Intel to develop and execute verification plans, run system-level simulations, and debug presilicon CPU designs.
MicroVision is hiring a Senior RTL Engineer to design, implement, verify, and bring-up FPGA/RTL features for market-leading automotive LiDAR systems.
Intel is hiring a seasoned CPU RTL Design Engineer to drive RTL development, optimization, and microarchitectural specification for cutting-edge processor IP.
Lead verification for next-generation space-qualified ASICs and FPGAs on SpaceX's Starshield program, developing SystemVerilog/UVM testbenches, driving coverage closure, and supporting pre/post-silicon bring-up.
Lead and grow a chiplet verification team at Intel, driving verification strategy and execution for complex ASIC/SoC products using advanced verification methodologies.
Lead power analysis and low‑power RTL optimization efforts at Intel to reduce dynamic and leakage power and improve overall CPU power efficiency.
Senior ASIC Design Engineer for Starshield to architect, implement, verify, and bring up high-performance ASIC/FPGA designs that support national security space and ground systems.
Lead the architecture, RTL, verification, and silicon bring-up of mixed-signal ASICs that power Atom Computing’s neutral-atom quantum computers while shaping the long-term silicon roadmap.
Lead verification strategy and SystemVerilog/UVM environment development for Marvell's Photonic Fabric SoCs, ensuring functional correctness through rigorous verification and automation.
Lead development of verification tooling and CI infrastructure to accelerate High-Speed IO ASIC verification for NVIDIA's GPU teams.
Intel is hiring a Design Engineer focused on neuromorphic computing to develop RTL, prototype on FPGA/emulation platforms, and collaborate across architecture, verification, and software teams to bring neuro-inspired silicon to product readiness.
Lead the design and delivery of high-performance, space-qualified ASICs and FPGAs for SpaceX's Starshield national security programs.
Cadence is hiring a Senior Principal IC Design Verification Application Engineer to lead customer-facing verification solutions using Xcelium and Verisium, solving complex verification challenges for top semiconductor customers.
Lead Applications Engineer to provide front-line technical expertise and customer-facing support for Cadence’s Palladium emulation and Protium FPGA prototyping platforms.
Senior Application Engineer for emulation and FPGA prototyping to deliver customer-facing technical support, develop acceleration/prototyping flows, and drive design wins for Cadence’s Palladium and Protium platforms.
Join Cadence’s elite verification field team to lead emulation and FPGA prototyping deployments, drive technical evaluations, and deliver customer-facing solutions using Palladium and Protium.
SpaceX Starshield is hiring a Principal ASIC Design Verification Engineer to lead SystemVerilog-based verification, drive test plans and regressions, and support pre- and post-silicon validation of next-generation space-qualified ASICs.
SpaceX Starshield is hiring a Senior ASIC Design Engineer to develop and verify next-generation FPGA/ASIC solutions for national-security space and ground systems.
SpaceX Starshield is hiring a Sr. ASIC Design Verification Engineer to lead SystemVerilog-based verification and validation of next-generation space and ground ASICs/FPGAs for national security applications.
Senior RTL Design Engineer needed to develop and optimize RTL for Intel's next-generation CPU microarchitecture, driving high-performance and power-efficient processor features.
Validate and characterize next-generation mixed-signal preamp chips at Western Digital using RF test gear, automation scripting, and hands-on board-level debugging as part of an early-career development program.
Intel's ACE organization is hiring a Design Verification Engineer to create and execute UVM/SystemVerilog verification environments for next-generation CPU designs.
Mythic seeks a Senior Silicon Emulation Engineer to develop and operate large-scale emulation platforms for AI accelerators and enable early software and performance validation before silicon.
Mach Industries is hiring an FPGA Engineer to architect, implement, and verify FPGA/SoC logic that powers next-generation autonomous defense platforms in Huntington Beach.
CX2 is hiring an FPGA Engineer in El Segundo to develop and optimize FPGA-based solutions for real-time radar, EW, and communications systems.
How much do systemverilog jobs pay?
Below 50k*
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50k-100k*
1
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Over 100k*
34
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Top companies hiring for systemverilog jobs
- Intel 9
- SpaceX 6
- Cadence 5
- Analog Devices 2
- Hewlett Packard Enterprise 1
- Micron 1
- SEC 1
