Cadence Jobs

Senior Hardware Design Engineer role focused on ASIC/FPGA/SoC design, verification, and physical implementation for a cleared government-contractor environment.

Lead commercial operations for IFS Loops to build a repeatable GTM engine, drive adoption in the installed base, and scale revenue through disciplined execution and cross-functional governance.

Marvell is hiring a Staff Analog Layout Engineer in Santa Clara to lead layout and verification of high-speed and precision analog IP using Cadence Virtuoso across multiple process nodes.

Lead end-to-end physical design for cutting-edge SoCs at a high-growth Series C space company building the most powerful satellites in orbit.

Lead the architecture, RTL, verification, and silicon bring-up of mixed-signal ASICs that power Atom Computing’s neutral-atom quantum computers while shaping the long-term silicon roadmap.

Elevate Semiconductor is hiring a Senior Analog Design Engineer in San Diego to lead design and optimization of high-performance analog CMOS circuits for ATE products.

Senior engineer to build and own SPICE simulation flows and Virtuoso-based CAD automation that accelerate analog/mixed-signal design productivity and improve simulation-to-silicon correlation.

Inclusive & Diverse

Rise from Within

Mission Driven

Diversity of Opinions

Work/Life Harmony

Growth & Learning

Transparent & Candid

Customer-Centric

Snacks

Onsite Gym

Family Coverage (Insurance)

Medical Insurance

Dental Insurance

Vision Insurance

Mental Health Resources

Life insurance

Disability Insurance

Health Savings Account (HSA)

Flexible Spending Account (FSA)

Learning & Development

Paid Time-Off

401K Matching

Maternity Leave

Paternity Leave

Lead frame cellset integration and validation for Intel Foundry, ensuring accurate scribeline layouts and tapeout integrity across lithography and metrology processes.

Inclusive & Diverse

Rise from Within

Mission Driven

Diversity of Opinions

Work/Life Harmony

Growth & Learning

Transparent & Candid

Customer-Centric

Snacks

Onsite Gym

Family Coverage (Insurance)

Medical Insurance

Dental Insurance

Vision Insurance

Mental Health Resources

Life insurance

Disability Insurance

Health Savings Account (HSA)

Flexible Spending Account (FSA)

Learning & Development

Paid Time-Off

401K Matching

Maternity Leave

Paternity Leave

Become a key contributor on Intel's DTP team building and automating density/fill solutions and PDK fill components to ensure manufacturability at advanced semiconductor nodes.

Cadence is hiring a Solutions Architect (AE) to lead PDK/technology file development and provide technical and business-facing support to semiconductor customers working on advanced process nodes.

Radiant is hiring a Senior Electrical Engineer to own multilayer PCB design and hardware architecture for robust reactor control systems at its El Segundo headquarters.

Entry-level Electrical Engineer (PCB Design) to support schematic capture, multilayer PCB layout, bring-up, and validation for reactor control systems at Radiant’s El Segundo HQ.

Senior-level analog/mixed-signal IC design role at a leading semiconductor company working on high-speed circuits, PLLs/clock generation, and data converters.

Senior Electrical Engineer (Manufacturing Test) to design PCBA-based test platforms, fixtures, and data-acquisition systems for high-quality production at Anduril's Costa Mesa/Santa Ana facilities.

Lead the microarchitecture, RTL design, and front-to-back implementation of complex SoC subsystems at a VC-backed semiconductor startup advancing next-generation chiplet solutions.

Tenstorrent is hiring a Signal Integrity Engineer to drive high-speed PCB and package design, simulation, and validation for next-generation AI processors across Santa Clara, Austin, or Toronto.

Mythic seeks a Senior Silicon Emulation Engineer to develop and operate large-scale emulation platforms for AI accelerators and enable early software and performance validation before silicon.

Lead and grow the Package Design team to deliver HVM-ready IC packaging solutions (FCBGA/FCCSP, multi-die, chiplets) that enable Astera Labs' PCIe, CXL, and Ethernet connectivity products.

A high-ownership technical lead role to design, simulate, layout, and drive first-silicon learning for highly integrated silicon photonic ICs at an early-stage photonics company.

Tacit seeks a PhD-level Antenna Engineering Intern to design, simulate, and validate advanced wireless sensing antennas within a fast-moving hardware startup in San Francisco.

Marvell is hiring a Senior Staff Analog Layout SRAM Engineer in Burlington, VT to lead SRAM memory layout and sign-off verification efforts and drive automation and quality across custom memory designs.

Western Digital seeks an experienced Chief of Staff to the SVP of Product Management & Emerging Businesses to drive strategic execution, operating cadence, and cross-functional alignment across the organization.

Etched is looking for an experienced Component Engineer in San Jose to drive component evaluation, qualification, and lifecycle risk management for its next-generation AI inference hardware.

Experienced DRAM design engineer needed to drive circuit design, simulation, and layout leadership for advanced memory products at Micron's Richardson site.

CDW is hiring a remote Professional Services Operations Specialist to own reporting, resource planning, and operational execution for the Professional Services organization.

Lead Hardware Design Engineer to own end-to-end power delivery hardware architecture and validation for PowerLattice's chiplet-based SoC platforms in Chandler, AZ.