Lead Hardware Design Engineer - Power Delivery

About Us

PowerLattice is a well-funded semiconductor startup backed by leading Silicon Valley venture capital firms. We are developing a groundbreaking chiplet solution for a fundamental shift in how high-performance chips are powered, paving the way for the next generation of AI and advanced computing. We are the first to offer a tiny device that can be integrated into a SoC package.

About the Role

We are seeking a Lead Hardware Design Engineer - Power Delivery to spearhead the physical implementation and hardware architecture of our power delivery solutions based on PowerLattice chiplets. This senior leadership role is responsible for the end-to-end hardware lifecycle, from initial schematic entry to complex PCB design and system bring-up. You will serve as a primary technical authority, bridging the gap between internal silicon design and the physical hardware platforms that enable our tier-one customers to succeed

Key Responsibilities

• End-to-End Hardware Development: Lead the design and development of complex hardware platforms, including schematic entry, PCB layout, and Bill of Materials (BOM) management.

• Advanced PCB Design: Drive high-density, multi-layer PCB design focused on Power Delivery Networks (PDN), ensuring integrity across substrates and advanced packaging.

• System Architecture: Define hardware architectures for reference platforms and validation boards, integrating multi-chiplet SoC solutions and high-performance power converters. Design multi-phase buck converters for server/AI hardware platforms.

• Customer Enablement: Assist customers in optimizing their PDN designs using PowerLattice’s design kits and proprietary chiplet technology.

• Validation & Bring-up: Lead the physical bring-up and debugging of complex subsystems, utilizing advanced instrumentation to resolve power/reset timing and silicon anomalies.

• Technical Leadership: Act as a mentor and project lead, coordinating with cross-functional teams in SIPI, packaging, and manufacturing to ensure product success.

Minimum Qualifications

This is a Hybrid role requiring 3 days a week onsite at our Chandler, AZ. While we are primarily seeking candidates in Chandler, remote flexibility may be considered for exceptional candidates.

• Experience: 10+ years of experience in hardware design, specifically focused on power integrity, board-level power distribution, or high-performance SoC platforms.

• Design Expertise: Extensive hands-on experience with Schematic Capture and PCB Design tools (e.g., Cadence Allegro, OrCAD, or Altium Designer).

• Power Integrity: Deep proficiency in extracting, building, and validating electrical models for SoC packages and power delivery networks.

• Advanced Packaging: Strong understanding of package-level SI/PI, including substrates, interposers, and 2.5D/3D packaging technologies.

• Communication: Excellent verbal and written skills, with the ability to maintain professional discretion when handling sensitive technical data.

Bonus Points

• Prior experience at major processor or ASIC companies.

• Proven experience as engineering or project lead in a related technical area

• Experience with HW/FW/SW telemetry data flow, dynamic clock voltage scaling architecture, thermal/power limits management.

• Experience with design of multi-phase buck converter for server/AI hardware platforms

Compensation & Benefits

Anticipated Base Salary: $200,000 - $250,000 (Dependent on experience)

• Stock option grant.

• Comprehensive health, dental, vision, and 401(k) package.