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Manager, Package Design Engineering

Astera Labs delivers rack-scale AI connectivity solutions and is hiring a Manager, Package Design Engineering to lead and scale the Package Design team in San Jose. The role owns end-to-end IC packaging delivery — from architecture and feasibility through tape-out and production ramp — and requires cross-functional collaboration with silicon, SIPI, board, manufacturing partners, and OSATs to enable high-performance PCIe/CXL/Ethernet connectivity products.

Skills

  • Proven end-to-end IC package design experience using Cadence Allegro APD/SiP
  • Delivered HVM-ready FCBGA/FCCSP packages
  • Experience with high-speed SerDes and protocols (PCIe Gen5/6/7, CXL, Ethernet 100G+)
  • Deep knowledge of substrate technologies, stack-ups, routing constraints, assembly and SI/PI fundamentals
  • Proven collaboration with OSATs and substrate vendors through development and production ramp
  • Leadership experience managing package design teams and driving multi-disciplinary execution

Responsibilities

  • Build, mentor, and scale a high-performing package design engineering team with clear ownership and execution flows
  • Establish design templates, standards, and best-known methods across concurrent programs
  • Own end-to-end package design delivery from concept feasibility through tape-out and production ramp for FCBGA/FCCSP, monolithic, multi-die, and chiplet-based designs
  • Define and review substrate stack-ups, pad stacks, routing strategies, and design constraints to meet electrical, thermal, mechanical, and manufacturability requirements
  • Lead design reviews, audits, and issue resolution during bring-up and production ramp
  • Drive technical tradeoffs across performance, cost, yield, and schedule to ensure timely, high-quality design closure
  • Partner with SIPI, silicon architecture, system/board design, and product teams for chip-package-board co-design
  • Collaborate with substrate vendors and OSATs to ensure manufacturability and alignment with technology roadmaps
  • Support adoption of advanced packaging technologies (2.5D/3D, chiplet, CPO/CPC) and scale automation/methodologies

Education

  • Bachelor's degree in Electrical Engineering, Materials Science, or related field required
  • Master's degree in Electrical Engineering or related field preferred

Benefits

  • Competitive base salary and potential equity (company is publicly traded)
  • Comprehensive health, dental, and vision insurance
  • 401(k) retirement plan
  • Paid time off and parental leave
  • Professional development and training opportunities
  • Collaborative, innovation-driven work environment
To read the complete job description, please click on the ‘Apply’ button
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CEO of Astera Labs
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Jitendra Mohan
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Average salary estimate

$247500 / YEARLY (est.)
min
max
$230000K
$265000K

If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.

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Our Values: Our team values are integral to who we are and how we operate as a company. Customer Focus: We are intensely focused on customers' needs. Deliver Results: We execute in order to consistently prove our promise; on time, according to s...

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DEPARTMENTS
SENIORITY LEVEL REQUIREMENT
TEAM SIZE
SALARY RANGE
$230,000/yr - $265,000/yr
EMPLOYMENT TYPE
Full-time, onsite
DATE POSTED
March 29, 2026
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