Timing Jobs
Browse 18 exciting jobs hiring in Timing now. Check out companies hiring such as Analog Devices, Vector Atomic, MicroVision in Oxnard, St. Paul, Anaheim.
Analog Devices is hiring a Staff AI/ML Digital Design Engineer to lead complex RTL design work while embedding AI/ML-driven automation into digital design flows.
Support deployment, troubleshooting, and repair of advanced quantum timing and photonics systems as a customer-facing Field Support Engineer responsible for installations, field diagnostics, and service process development.
Analog Devices is hiring a Digital Design Engineer to architect and verify low-power, high-speed SerDes digital IP and mixed-signal block designs for advanced semiconductor products.
MicroVision is hiring a Senior RTL Engineer to design, implement, verify, and bring-up FPGA/RTL features for market-leading automotive LiDAR systems.
Lead RTL‑to‑GDSII implementation and advance physical design methodology for high‑performance processor and networking ASICs at Marvell's Westborough physical design team.
Senior ASIC Design Engineer for Starshield to architect, implement, verify, and bring up high-performance ASIC/FPGA designs that support national security space and ground systems.
Lead full-chip and block-level physical implementation of advanced SoCs that power K2's high-power satellites, from synthesis through GDSII and sign-off.
Lead end-to-end physical design for cutting-edge SoCs at a high-growth Series C space company building the most powerful satellites in orbit.
AECOM is seeking an Entry Level Traffic Engineer in Indianapolis to assist with traffic analysis, CAD drafting, data collection and supervised design tasks on transportation projects.
An internship opportunity at Intel to contribute to circuit design, simulation, and verification for digital and/or analog systems while working within the Intel Foundry organization.
Lead the design and delivery of high-performance, space-qualified ASICs and FPGAs for SpaceX's Starshield national security programs.
Senior Application Engineer for emulation and FPGA prototyping to deliver customer-facing technical support, develop acceleration/prototyping flows, and drive design wins for Cadence’s Palladium and Protium platforms.
SpaceX Starshield is hiring a Senior ASIC Design Engineer to develop and verify next-generation FPGA/ASIC solutions for national-security space and ground systems.
Senior RTL Design Engineer needed to develop and optimize RTL for Intel's next-generation CPU microarchitecture, driving high-performance and power-efficient processor features.
KRQE News 13 is looking for an experienced News Producer to craft compelling newscasts, manage story order and timing, and produce content for broadcast and digital audiences in Albuquerque.
Research-focused internship at Cadence to develop advanced gate models for timing analysis, requiring Python scripting and circuit simulation expertise.
CX2 is hiring an FPGA Engineer in El Segundo to develop and optimize FPGA-based solutions for real-time radar, EW, and communications systems.
Lead CPU Logic Design Engineer role at Intel driving RTL and microarchitecture development to deliver high-performance, low-power CPU features for SoC integration.
